Documents

Computing on soc architecture

INFN COSA Project

Links

Talks:

COSA at the CCR Workshop in L.N.G.S., L'Aquila, Italy 

COSA at the CCR Meeting in Torino, Italy

COSA at the PDP 2017 Euromicro International Conference, Saint Petersburg

COSA at the CCR Workshop in La Biodola, Italy

COSA at the Seventh INFN International School in Bertinoro, Italy

COSA at the INFN CCR Workshop in Frascati, Italy

COSA talk at CERN GDB

COSA talk at HEPIX Spring Workshop in Oxford


COSA github Benchmark Page


Papers:


Implementing a space-aware stochastic simulator on low-power architectures: a systems biology case study, Morganti L., Corni E., Ferraro A., Cesini D., D'Agostino D., Merelli I., 25th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP) 2017


Low-power architectures for miRNA-target genome wide analysis, Beretta S., Morganti L., Corni E., Ferraro A., Cesini D., D'Agostino D., Milanesi L., Merelli I., 25th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP) 2017


X-Ray Computed Tomography Applied to Objects of Cultural Heritage: Porting and Testing the Filtered Back-Projection Reconstruction Algorithm on Low Power Systems-on-Chip, Corni E, Morganti L, Morigi MP, Brancaccio R, Bettuzzi M, Levi G, Peccenini E, Cesini D, Ferraro A, 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP) 2016, 369-372, 2016


Evaluating Systems on Chip through HPC Bioinformatics and Astrophysics Applications, Morganti L, Cesini D, Ferraro A, 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP) 2016, 541-544, 2016

Power, Energy and Speed of Embedded and Server Multi-Cores applied to Distributed Simulation of Spiking Neural Networks: ARM in NVIDIA Tegra vs Intel Xeon quad-cores, Paolucci PS, Ammendola R, Biagioni A, Frezza O, Lo Cicero F, Lonardo A, Martinelli M, Pastorelli E, Simula F, Vicini P, arXiv:1505.03015, 2015


Architectural improvements and technological enhancements for the APEnet plus interconnect system, Ammendola R, Biagioni A, Frezza O, Lonardo A, Lo Cicero F, Martinelli M, Paolucci PS, Pastorelli E, Rossetti D, Simula F, Tosoratto L, Vicini P, JOURNAL OF INSTRUMENTATION, 10-, C02005, 2015


Hardware and Software Design of FPGA-based PCIe Gen3 interface for APEnet plus network interconnect system, Ammendola R, Biagioni A, Frezza O, Lo Cicero F, Lonardo A, Martinelli M, Paolucci PS, Pastorelli E, Rossetti D, Simula F, Tosoratto L, Vicini P, 21ST INTERNATIONAL CONFERENCE ON COMPUTING IN HIGH ENERGY AND NUCLEAR PHYSICS (CHEP2015), PARTS 1-9, 664-, 092017, 2015


​ASIP acceleration for virtual-to-physical address translation on RDMA-enabled FPGA-based network interfaces, Ammendola R, Biagioni A, Frezza O, Geurts W, Goossens G, Lo Cicero F, Lonardo A, Paolucci PS, Rossetti D, Simula F, Tosoratto L, Vicini P, FUTURE GENERATION COMPUTER SYSTEMS-THE INTERNATIONAL JOURNAL OF GRID COMPUTING AND ESCIENCE, 53-, 2015


Dynamic Many-process Applications on Many-tile Embedded Systems and HPC Clusters: the EURETILE programming environment and execution platforms, Paolucci PS, Biagioni A, Murillo LG, Rousseau F, Schor L, Tosoratto L, Vicini P, Journal of Systems Architecture, 2015


Energy-performance tradeoffs for HPC applications on low power processors, Calore E, Schifano SF, Tripiccione R, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 2015


Optimizing communications in multi-GPU Lattice Boltzmann simulations, Calore E, Marchi D, Schifano SF, Tripiccione R, Proceedings of the 2015 International Conference on High Performance Computing and Simulation, 2015